1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device with a plurality of insulating films and a plurality of electrode films alternately stacked therein, and a method for manufacturing the same.
2. Background Art
Conventionally, nonvolatile semiconductor memory devices such as flash memories have been fabricated by two-dimensionally integrating elements on the surface of a silicon substrate. In this type of flash memory, downscaling by decreasing the dimensions of each element is required to reduce cost per bit and increase memory capacity. However, such downscaling has been difficult in terms of cost and technology.
Numerous ideas for three-dimensionally integrating elements are proposed as techniques for breaking through the limit of integration. However, a three-dimensional device typically requires at least three lithography steps for each layer. Hence, cost increase associated with increased lithography steps cancels out cost reduction associated with decreased footprint on the silicon substrate. Thus, cost reduction is difficult despite three-dimensional construction.
In view of this problem, the present inventor and others proposed a simultaneously processed three-dimensional stacked memory (see, e.g., JP-A-2007-266143 (Kokai)). In this technique, electrode films and insulating films are alternately stacked on a silicon substrate to form a stacked body, and then through holes are simultaneously formed in this stacked body. A charge storage layer is formed on the side surface of the through hole, and silicon is buried inside the through hole to form a silicon pillar. Thus, a memory cell is formed at each intersection between the electrode film and the silicon pillar.
In this simultaneously processed three-dimensional stacked memory, information can be recorded by controlling the potential of each electrode film and each silicon pillar to transfer charge between the silicon pillar and the charge storage layer. In this technique, a plurality of electrode films are stacked on the silicon substrate to reduce the chip area per bit, achieving cost reduction. Furthermore, because the stacked body can be simultaneously processed to fabricate a three-dimensional stacked memory, increase in the number of stacked layers does not result in increasing the number of lithography steps, and cost increase can be limited.
However, the simultaneously processed three-dimensional stacked memory thus fabricated has a problem of increased interference between memory cells as its downscaling proceeds.